Get Smart

The FSB is not merely a bus anymore. Far more than a set of traces that run from one part of the motherboard to another, the FSB is part of the memory architecture, which includes caches, prefetchers, and other specialized functions. Taken together, the system is the Intel Advanced Smart Cache.

Designers long ago realized that software tends to operate on clusters of data and that some code is executed repeatedly. Performance is greatly enhanced if the data and instructions are held in high-speed cache memory, right on the processor chip. Intel architectures have a two-level cache scheme. The L1 data cache unit or DCU is closely tied to the processor core—each core in a multiprocessor chip has one. It allows the processor to deal with cache misses and enhances its ability to perform out-of-order execution.

A variety of buffers also help speed memory access efficiency. The Data Translation Lookaside Buffer (DTLB) in the Intel Core architecture is a two-level, hierarchical design. It converts virtual addresses that the processor can manipulate quickly into physical addresses for both loads and stores. The DTLB works in conjunction with on-chip Page Miss Handler logic, an important feature that causes the vast majority of page misses to be non-blocking, which means that the processor doesn’t have to do a page walk, and wait while the physical address is located. The Memory Ordering Buffer (MOB) lets the processor issue loads and stores speculatively and out of order. Out-of-order execution is vital to high performance because it lets the processor work on tasks further down the pipeline while the data for prior tasks is being fetched. The MOB ensures that the loads and stores have valid data, that speculative results are ignored, and that the physical writing to main memory happens in the most efficient manner.